features ? built using the advantages and compatibility of cmos and ixys hdmos tm processes ? latch-up protected over entire operating range ? high peak output current: 14a peak ? wide operating range: 4.5v to 35v ? -55 o c to 125 o c extended operating temperature standard ? high capacitive load drive capability: 15nf in <30ns ? matched rise and fall times ? low propagation delay time ? low output impedance ? low supply current applications ? driving mosfets and igbts ? motor controls ? line drivers ? pulse generators ? local power on/off switch ? switch mode power supplies (smps) ? dc to dc converters ixdn414pi / n414ci / n414yi / n414si ixdi414pi / i414ci / i414yi / i414si first release copyright ? ixys corporation 2004 general description the ixdi414/ixdn414 are high speed high current gate drivers specifically designed to drive the largest mosfets and igbts to their minimum switching time and maximum practical frequency limits. the ixdi/n414 can source and sink 14a of peak current, while producing voltage rise and fall times of less than 30ns, to drive the latest ixys mosfets & igbts. the input of the driver is compatible with ttl or cmos and is fully immune to latch up over the entire operating range. designed with small internal delays, a patent-pending circuit virtually eliminates transistor cross conduction and current shoot- through. improved speed and drive capabilities are further enhanced by very low, matched rise and fall times. the ixdn414 is configured as a non-inverting gate driver and the ixdi414 is an inverting gate driver. the ixdn414/ixdi414 family are available in standard 8 pin p-dip (pi), 5-pin to-220 (ci), to-263 (yi) and thermally enhanced 14-pin soic (si) surface-mount packages. figure 1 - ixdn414 14a non-inverting gate driver functional block diagram 14 ampere low-side ultrafast mosfet and igbtdrivers * patent pending n p out vcc in anti-cross conduction circuit * gnd gnd vcc ds99020b(08/04)
2 ixdn414pi / n414ci / n414yi / n414si ixdi414pi / i414ci / i414yi / i414si to220 (ci) to263 (yi) figure 2 - ixdi414 inverting 14a gate driver functional block diagram * patent pending pin description and configuration symbol function description vcc supply voltage positive power-supply voltage input. this pin provides power to the entire chip. the range for this voltage is from 4.5v to 35v. in input input signal-ttl or cmos compatible. out output driver output. for application purposes, this pin is connected via an external resistor to a gate of a mosfet/igbt. gnd ground the system ground pin. internally connected to all circuitry, this pin provides ground reference for the entire chip. this pin should be connected to a low noise analog ground plane for optimum performance. n p out vcc in anti-cross conduction circuit * gnd gnd vcc ordering information part number package type temp. range configuration ixdn414pi 8-pin pdip IXDN414SI 14-pin soic -55 c to 125 c ixdn414ci 5-pin to-220 -55 c to 125 c ixdn414yi 5-pin to-263 -55 c to 125 c non inverting ixdi414pi 8-pin pdip ixdi414si 14-pin soic -55 c to 125 c ixdi414ci 5-pin to-220 -55 c to 125 c ixdi414yi 5-pin to-263 -55 c to 125 c inverting 2: mounting or solder tabs on all packages are connected to ground vcc in nc gnd vcc out gnd out 1 2 3 4 8 7 6 5 i x d (1) 4 1 4 p i 8 pin dip (pi) i x d (1) 4 1 4 s i nc vcc in nc nc out vcc 1 2 3 4 14 13 12 11 10 9 8 5 6 7 nc nc gnd nc out gnd nc 14 pin soic (1) (1) notes 1: either "i" or "n";
3 ixdn414pi / n414ci / n414yi / n414si ixdi414pi / i414ci / i414yi / i414si parameter v alue supply voltage 40v all other pins -0.3v to v cc + 0.3v power dissipation t case 25 o c: to220 (ci), to263 (yi)* 12.5w power dissipation, t ambient 25 o c 8 pin pdip (pi), 14 pin soic to220 (ci) to263 (yi) 833mw 2w storage temperature -55 o c to 150 o c soldering lead temperature (10s) tab temperature (10s) 300 o c 260 o c unless otherwise noted, t a = 25 o c, 4.5v v cc 35v . all voltage measurements with respect to gnd. device configured as described in test conditions . electrical characteristics absolute maximum ratings (note 1) operating ratings symbol parameter test conditions min typ max units v ih high input voltage 4.5v v cc 18v 3.5 v v il low input voltage 4.5v v cc 18v 0.8 v v in input voltage range -5 v cc + 0.3 v i in input current 0v v in v cc -10 10 a v oh high output voltage v cc - 0.025 v v ol low output voltage 0.025 v r oh output resistance @ output high i out = 10ma, v cc = 18v 600 1000 m ? r ol output resistance @ output low i out = 10ma, v cc = 18v 600 1000 m ? i peak peak output current v cc is 18v 14 a i dc continuous output current 8 pin dip (pi) (limited by pkg power dissipation) to220 (ci), to263 (yi) 3 4 a a t r rise time (1) c l =15nf vcc=18v 22 27 ns t f fall time (1) c l =15nf vcc=18v 20 25 ns t ondly on-time propagation delay (1) c l =15nf vcc=18v 30 33 ns t offdly off-time propagation delay (1) c l =15nf vcc=18v 31 34 ns v cc power supply voltage 4.5 18 35 v i cc power supply current v in = 3.5v v in = 0v v in = + v cc 1 0 3 10 10 ma a a (1) see figures 3a and 3b specifications subject to change without notice note 1: operating the device beyond parameters with listed ?absolute maximum ratings? may cause permanent damage to the device. typical values indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. the guaranteed specifications apply only for the test conditions listed. exposure to absolute maximum rated conditions for extended periods may affect device reliability. caution: these devices are sensitive to electrostatic discharge; follow proper esd procedures when handling and assembling this component. parameter value maximum junction temperature 150 o c operating temperature range -55 o c to 125 o c thermal resistance (junction to case) to220 (ci) to263 (yi), 14 pin soic (si) 10 k/w thermal resistance (junction to ambient) 8-pin pdip (pi) 150 k/w 14-pin soic 120 k/w to-220 (ci), to-263 (yi) 62.5 k/w * subject to internal lead current limit i dc
4 ixdn414pi / n414ci / n414yi / n414si ixdi414pi / i414ci / i414yi / i414si figure 3a - characteristics test diagram figure 3b - timing diagrams non-inverting (ixdn414) timing diagram inverting (ixdi414) timing diagram 0v 5.0v 0v vcc ixdi414 ixdn414 0v vcc agilent 1147a current probe 15nf 10uf 25v 0v 5v 90% 10% 2.5v input vcc 0v 10% 90% output pw min t f t offdly t r t ondly input output 5v 90% 2.5v 10% 0v 0 v vcc 90% 10% t ondly t offdly t r t f pw min
5 ixdn414pi / n414ci / n414yi / n414si ixdi414pi / i414ci / i414yi / i414si typical performance characteristics max / min input vs. case temperature v cc =18v c l =15nf temperature ( o c) -60 -40 -20 0 20 40 60 80 100 max / min input (v) 1.6 1.8 2.2 2.4 2.6 2.8 3.2 2.0 3.0 maximum input low minimum input high fall time vs. load capacitance load capacitance (pf) 0k 5k 10k 15k 20k fall time (ns) 0 10 20 30 40 18v 8v 10v 12v 14v 16v rise time vs. load capacitance load capacitance (pf) 0k 5k 10k 15k 20k rise time (ns) 0 10 20 30 40 50 18v 8v 10v 12v 14v 16v rise and fall times vs. case temperature c l = 15 nf, v cc = 18v tem p erature ( c ) -40-20 0 20406080100120 time (ns) 0 5 10 15 20 25 30 35 40 t f t r rise time vs. supply voltage supply voltage (v) 8 1012141618 rise time (ns) 0 10 20 30 40 cl=15,000 pf 7,500 pf 3,600 pf fall time vs. supply voltage supply voltage (v) 8 1012141618 fall time (ns) 0 10 20 30 40 cl=15,000 pf 7,500 pf 3,600 pf fig. 4 fig. 5 fig. 6 fig. 7 fig. 8 fig. 9
6 ixdn414pi / n414ci / n414yi / n414si ixdi414pi / i414ci / i414yi / i414si supply current vs. load capacitance vcc=8v load capacitance (pf) 1k 10k 100k supply current (ma) 1 10 100 1000 50 khz 100 khz 500 khz 1 mhz 2 mhz supply current vs. load capacitance vcc=12v load capacitance (pf) 1k 10k 100k supply current (ma) 1 10 100 1000 50 khz 100 khz 500 khz 1 mhz 2 mhz supply current vs. frequency vcc=8v frequency (khz) 10 100 1000 10000 supply current (ma) 0.1 1 10 100 1000 2000 pf cl= 30 nf 5000 pf 15 nf supply current vs. frequency vcc=18v frequency (khz) 10 100 1000 10000 supply current (ma) 0.1 1 10 100 1000 2000 pf cl= 30 nf 5000 pf 15 nf supply current vs. frequency vcc=12v frequency (khz) 10 100 1000 10000 supply current (ma) 0.1 1 10 100 1000 2000 pf cl = 30 nf 5000 pf 15 nf supply current vs. load capacitance vcc=18v load capacitance (pf) 1k 10k 100k supply current (ma) 1 10 100 1000 50 khz 100 khz 500 khz 1 mhz 2 mhz fig. 13 fig. 15 fig. 11 fig. 12 fig. 14 fig. 16
7 ixdn414pi / n414ci / n414yi / n414si ixdi414pi / i414ci / i414yi / i414si propagation delay vs. input voltage c l =15nf v cc =15v input voltage (v) 24681012 propagation delay (ns) 0 10 20 30 40 50 t ondly t offdly propagation delay vs. supply voltage c l =15nf v in =5v@1khz supply voltage (v) 8 1012141618 propagation delay (ns) 0 10 20 30 40 50 t ondly t offdly p channel output current vs. case temperature v cc =18v c l =.1uf temperature ( o c) -40-20 0 20406080100 p channel output current (a) 12 13 14 15 16 n channel output current vs. case temperature v cc =18v c l =.1uf temperature ( o c) -40-200 20406080100 n channel output current (a) 14 15 16 17 quiescent supply current vs. case temperature v cc =18v v in =5v@1khz tem p erature ( o c ) -40-200 20406080 quiescent supply current (ma) 0.50 0.52 0.54 0.56 0.58 0.60 propagation delay vs. case temperature c l = 2500pf, v cc = 18v tem p erature ( c ) -40-200 20406080100120 time (ns) 10 15 20 25 30 35 40 45 50 t offdly t ondly fig. 18 fig. 20 fig. 22 fig. 17 fig. 19 fig. 21
8 ixdn414pi / n414ci / n414yi / n414si ixdi414pi / i414ci / i414yi / i414si low-state output resistance vs. supply voltage supply voltage (v) 10 15 20 25 low-state output resistance (ohms) 0.2 0.4 0.6 0.8 0.0 1.0 8 high state output resistance vs. supply voltage supply voltage (v) 10 15 20 25 high state output resistance (ohm) 0.2 0.4 0.6 0.8 0.0 1.0 8 v cc vs. p channel output current c l =.1uf v in =0-5v@1khz vcc 10 15 20 25 p channel output current (a) -24 -22 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 8 vcc vs. n channel output current c l =.1uf v in =0-5v@1khz vcc 10 15 20 25 n channel output current (a) 0 2 4 6 8 10 12 14 16 18 20 22 24 8 enable threshold vs. supply voltage supply voltage (v) 8 101214161820222426 enable threshold (v) 0 2 4 6 8 10 12 14 fig. 23 fig. 24 fig. 25 fig. 26 fig. 27
9 ixdn414pi / n414ci / n414yi / n414si ixdi414pi / i414ci / i414yi / i414si when designing a circuit to drive a high speed mosfet utilizing the ixdn414/ixdi414, it is very important to observe certain design criteria in order to optimize performance of the driver. particular attention needs to be paid to supply bypassing , grounding , and minimizing the output lead inductance . say, for example, we are using the ixdn414 to charge a 5000pf capacitive load from 0 to 25 volts in 25ns . using the formula: i= ? v c / ? t, where ? v=25v c=5000pf & ? t=25ns we can determine that to charge 5000pf to 25 volts in 25ns will take a constant current of 5a. (in reality, the charging current won?t be constant, and will peak somewhere around 8a). supply bypassing in order for our design to turn the load on properly, the ixdn414 must be able to draw this 5a of current from the power supply in the 25ns. this means that there must be very low impedance between the driver and the power supply. the most common method of achieving this low impedance is to bypass the power supply at the driver with a capacitance value that is a magnitude larger than the load capacitance. usually, this would be achieved by placing two different types of bypassing capacitors, with complementary impedance curves, very close to the driver itself. (these capacitors should be carefully selected, low inductance, low resistance, high-pulse current- service capacitors). lead lengths may radiate at high frequency due to inductance, so care should be taken to keep the lengths of the leads between these bypass capacitors and the ixdn414 to an absolute minimum. grounding in order for the design to turn the load off properly, the ixdn414 must be able to drain this 5a of current into an adequate grounding system. there are three paths for returning current that need to be considered: path #1 is between the ixdn414 and its load. path #2 is between the ixdn414 and its power supply. path #3 is between the ixdn414 and whatever logic is driving it. all three of these paths should be as low in resistance and inductance as possible, and thus as short as practical. in addition, every effort should be made to keep these three ground paths distinctly separate. otherwise, the returning ground current from the load may develop a voltage that would have a detrimental effect on the logic line driving the ixdn414. output lead inductance of equal importance to supply bypassing and grounding are issues related to the output lead inductance. every effort should be made to keep the leads between the driver and it?s load as short and wide as possible. if the driver must be placed farther than 2? (5mm) from the load, then the output leads should be treated as transmission lines. in this case, a twisted-pair should be considered, and the return line of each twisted pair should be placed as close as possible to the ground pin of the driver, and connected directly to the ground terminal of the load. supply bypassing, grounding practices and output lead inductance
10 ixdn414pi / n414ci / n414yi / n414si ixdi414pi / i414ci / i414yi / i414si ixys semiconductor gmbh edisonstrasse15 ; d-68623; lampertheim tel: +49-6206-503-0; fax: +49-6206-503627 e-mail: marcom@ixys.de ixys corporation 3540 bassett st; santa clara, ca 95054 tel: 408-982-0700; fax: 408-496-0670 e-mail: sales@ixys.net www.ixys.com 8-pin dip case outline (ixd_414pi) 14-pin soic case outline (ixd_414si) 5-leaded to-220 case outline (ixd_414ci) 5-leaded to-263 case outline (ixd_414yi)
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